Dow Corning announced that it has joined nanoelectronics research center imec to advance 3-D integrated circuit (IC) packaging technologies that stack IC chips in vertical 3-D architectures. The announcement was made Monday at Semicon West in San Francisco. By integrating multiple chips into a single package, 3-D IC technology promises to reduce form factor and power consumption, and increase bandwidth to enable more efficient inter-chip communication for next-generation microelectronic devices. Before 3-D IC fabrication can be broadly adopted, it will require advances in materials and processing technologies. Imec is currently tackling the key challenge of bonding the device wafer to a carrier wafer before wafer thinning and safely debonding the thin wafer after backside processing is completed. This was Dow Corning’s goal when designing its temporary bonding solution, which aims at simple processing using a bilayer concept comprising an adhesive and release layer. The technology also enables room-temperature bonding and debonding processes based on standard manufacturing methods. In collaboration with imec, Dow Corning will explore its temporary bonding CMOS-compatible solution for 3-D through-silicon-via (TSV) semiconductor packaging. The partnership will aim to further expand the technology’s ability to achieve simple, cost-effective bonding-debonding techniques compatible with standard manufacturing methods. “Imec’s precompetitive programs are an essential platform for industry leaders to share the risk and cost of advanced research,” said Eric Beyne, 3-D System Integration program director at imec. “We look forward to collaborating closely with our newest member organization as we drive the next stage of 3-D integration, and help ensure compatibility of the proposed thin wafer carrier solution with advanced, sub-10-nm CMOS device technologies.” For more information, visit: www.dowcorning.com