The goal of photonics is to use light to perform functions traditionally handled by electronics, such as communications, data transmission, and information processing. Photonics as a practical endeavor began with the invention of the laser in 1960. While inventions such as fiber optics for transmitting information helped spur the broad adoption of photonics technology in the telecommunications industry, photonics is now used in a wide range of technology applications, including medical diagnostics, biological and chemical detection, and manufacturing. During the 2000s, silicon photonics witnessed a ramp-up of investment in research and development, and the launch of multiple initiatives (AIM Photonics, COSMICC, and PETRA) to support these efforts. The global silicon photonics market is currently worth approximately $774.1 million and is expected to grow at a rapid rate of 20.8 percent between 2018 and 20231. The factors driving the growth of this market include price, capability, and size. As the price of silicon photonics technology continues to fall, demand is significantly increasing across multiple vertical industries. While silicon photonics designs contain components that look far different from traditional integrated circuit Manhattan layouts, they will require the same level of industry support to achieve mainstream production. Courtesy of Mentor, a Siemens Business. The cost of manufacturing photonics devices has limited their commercial availability, however. Silicon foundries have been successfully manufacturing silicon wafers in large volumes for years. These large volumes bring down costs, making silicon-based electrical integrated circuits (ICs) both affordable and profitable. At the same time, the development of design rule decks and process design kits (PDKs) helped standardize and optimize the design and verification of ICs across the industry, making it practicable and profitable for design companies to create the vast collection of ICs and intellectual property (IP) that exists in the market today. As it turns out, silicon surrounded by silicon oxide makes an almost ideal waveguide material. This means optical signals can travel through it with very little degradation, which is a critical factor in creating marketable silicon photonics designs. While we certainly have had successes over the past decade, why haven’t silicon photonic ICs (PICs) been more readily adopted on a larger scale? With all their advantages (transmission speed, low power usage, older proven processes, etc.), combined with the cost efficiencies of silicon wafer production, why haven’t they taken over the market yet? The basic answer: The scaling enabled through silicon foundries is built on and tailored to transistor-based technologies. One part of this is simply inertia. Foundries have a lot of experience and success tied into the Moore’s law model of ICs. While a 7-nm process today is very different from, say, a half-micron process 20 or 30 years ago, the improvements were achieved incrementally with each new node. It was always easier and cheaper to slightly modify existing mechanisms and processes than to start from scratch with something completely new. However, Moore’s law is now limping along. Yes, we can safely say there will be a 3-nm node, but it won’t bring the performance or area benefits that previous node shrinks accomplished, and it will for sure come with a hefty price tag. This implies an opportunity for an inflection in the market. But what will PICs need (other than the opportunity) to be successful on anything resembling the scale ICs have achieved? One answer lies in the standardization and optimization achieved by ICs. We need to replicate the machine that is the fabless infrastructure to work for a photonics-based world. This is easier said than done. But we can begin by taking a closer look at that infrastructure and its history to understand the effort required. Design flow Let’s consider what a fabless IC team receives from the foundry when designing a system on a chip (SoC). First, there is the PDK. The PDK essentially represents an implied contract that the appropriate electronic design automation (EDA) software tools, if used appropriately, will work to enable a manufacturable, operable design in the target process. At the heart of the PDK are the design rules, which define the manufacturing requirements for physical layouts. Design rule checking (DRC) ensures that the geometries created in a layout can be manufactured in the given foundry process. To support the design rules, the foundries must also declare which layers on an incoming GDS or OASIS file are used for which process steps used to create the appropriate masks. The next part of the PDK is the device models. Foundries are experts at transistor science. They meticulously characterize exactly how a transistor will perform in a given construct. As long as the designers build the transistors correctly, they can have confidence that the devices will perform as designed. But device models alone are insufficient for scaling. If designers had to focus on making sure every single transistor in the layout was assembled correctly, it would take eons to design the multibillion transistor SoCs created today. To enable this scaling, the PDKs add more information. First are parameterized cells (PCells). PCells allow the designer to select among a set of known and allowed parameters that can be modified within a range to enable different electrical behaviors for a transistor or a set of transistors. More importantly, these parameters can be driven through a predetermined and characterized design in the form of a circuit schematic. This schematic-driven design approach allows the designer to focus on design intent rather than on physical layout, greatly improving throughput. To further simplify the process, the PDK provides schematic symbols with allowed parameters, which designers can use to ensure their intended design can be achieved with the building blocks provided. But, even this is not enough. To go further, the foundries also provide parameterized standard cell libraries. These libraries represent commonly used logical gates and other relatively simple building blocks. The foundries also provide larger IP blocks and/or characterize and approve IP from third-party providers for components such as memories and processors. Theoretically, SoC designers can combine any or all of these to their liking and can be confident in their performance. But even this is not so easy. How do we know how well these pieces will perform together? This is where the digital design flow truly blossoms. Standard cells and IP come with timing libraries to give designers an idea of how they will behave when combined in a layout. Rather than detailed analysis, these timing libraries provide corners, which indicate the component’s behaviors under certain conditions. With the addition of some parameters, typically in the form of LEF libraries and tech files, these libraries can be used to direct a design flow that can both validate timing and also drive layout through place and route (P&R) tools. Yet even with all of this, an IC design flow is far from push-button, and it is still possible and relatively easy to make a mistake that results in yield or reliability problems. Given their overall history of success, though, you can see why designers are reluctant to abandon all this infrastructure and security. What does that mean for silicon photonics? It means the development of similar tools and components is essential to integrating PICs into the traditional IC design and verification processes, starting with the development of a photonics PDK. Actually, despite the challenges, good progress has been made toward achieving this goal. Even though the GDS and OASIS file formats do not natively support the curved structures common in PICs, and traditional DRC verification of these structures results in thousands of false errors, successful methods exist that allow a dedicated DRC run to check PIC layouts for real problems without flagging false errors. New process models Although true precharacterized photonics devices complete with a PCell definition are not yet a reality, they are coming soon. The ability to create such PCells can be achieved through the use of Python-based PCells (PyCells), or by using photonic design tools2,3,4. Traditional circuit verification tools can perform simple device black-box-style layout versus schematic (LVS) verification to ensure no shorts or opens exist in the generated layout, and they can pass the rendered optical design as extracted from the layout to optical simulators5,6. Design tools are also available that enable manual layout of integrated photonic designs, and integrated electrical/photonic layout automation tools are on their way. The resulting designs will be correct by construction and fit into an OpenAccess design flow. Together, these tools and processes represent a significant advancement that can help lead photonics designers away from focusing on device component differentiation toward designing based on known and precharacterized structures. The EDA industry realizes there are still big hurdles to overcome. Foundry partners are transistor experts, but they are far from optical experts. With an appropriate process model, which can be generated based on post-silicon measurements, we can predict how the drawn PIC layout will render through the manufacturing steps. We can automatically capture the differences between the intended layout shapes and the final form of the manufactured shapes. In this way, we can enable a foundry or a design team to characterize a device by generating layouts across multiple versions of possible physical parameters to determine how the differences will impact optical behavior. From this characterization, a better understanding of allowable combinations of allowable parameters will eventually enable the generation of certified/qualified PCells for PICs. Unlike the transistor, for which the electrical behavior is largely characterized by width and space, it is far more difficult to verify the intended electrical behavior of an optical device based on its layout, or even its silicon image, without doing a full simulation. Fortunately, this may not be necessary. The idea behind LVS device verification is to ensure that the layout adequately represents the intent. An alternative approach is simply to re-render the intentional shape to the placement in context. If no changes are found, then designers know the placed device matches the intended device. Several approaches can be used for this comparison, from complex pattern matching to regenerating based on the optical equations. But there is still one last issue to consider: how to successfully combine photonics and electronics components. In the ideal case, designers would put the required electrical and photonics components together on the same die. But, photonics components are often quite large compared to their electrical cousins, and they do not need advanced node processes. If designers needed electronics capabilities that are only enabled by advanced nodes to drive the photonics components, they would end up using a lot of very expensive area for the photonics components, making the final SoC price-prohibitive. In fact, given the large size of photonics components, trying to combine them with electronic components on one chip may also drive the die size up, further increasing costs. The obvious solution is multi-die packaging, and the news in that regard is quite good. Significant progress has been achieved with foundries and outsourced assembly and test (OSAT) companies in the development of PDK-like approaches to simplify and reduce the risks of package design and verification. In fact, TowerJazz, a leading-edge foundry in silicon photonics production, recently released its initial silicon photonics PDK. Customers targeting TowerJazz’s PH18 silicon photonics process now have the same high level of confidence that they are constructing physically correct silicon photonics devices as they have always had for CMOS devices7. Silicon photonics offers the promise of blazing-fast data transmission and high bandwidth coupled with low power consumption, which is essential for today’s high-performance computing, telecommunications, military, defense, aerospace, medical, and research applications. To realize this promise, however, design companies must receive the same level of support provided by foundries and EDA suppliers for the design and verification of ICs. Fortunately, the prognosis is good! The industry is actively engaging between foundries, designers, EDA suppliers, and OSATS, with commitments to continue and expand on the progress achieved thus far. The ultimate goal is to attain the inexpensive and scalable platform needed to move silicon photonics to a true production design offering. References 1. MarketsandMarkets (February 2018). Silicon photonics market by product (transceiver, switch, variable optical attenuator, cable, sensor), application (data center, telecommunications, military & defense, medical and life sciences, sensing), component, and geography — global forecast to 2023. www.marketsandmarkets.com/Market-Reports/silicon-photonics-116.html. 2. Python Software Foundation. Python programming language. www.python.org. 3. PhoeniX Software. OptoDesigner platform for integrated optics and photonic chip design. www.phoenixbv.com/product.php?submenu=dfa&subsubmenu=3&prdgrpID=3. 4. Luceda Photonics. IPKISS.eda framework for the design and the design management of integrated photonics chips. www.lucedaphotonics.com/en/product/ipkiss-eda. 5. Mentor, a Siemens Business. Calibre nmLVS layout vs. schematic physical verification. www.mentor.com/products/ic_nanometer_design/verification-signoff/circuit-verification/calibre-nmlvs. 6. Lumerical. Interconnect photonic integrated circuit design and analysis environment. www.lumerical.com/tcad-products. 7. Mentor, a Siemens Business. 2018. TowerJazz launches initial silicon photonics design kit based on the Mentor Calibre nmPlatform. March 13, 2018. www.mentor .com/company/news/siemens-mentor-towerjazz-launches-initial-silicon-photonics-design-kit-based-on-the-mentor-calibre-nmplatform.