Researchers from the Fraunhofer Institute for Laser Technology (Fraunhofer ILT), in collaboration with colleagues from Fraunhofer ISIT and IST, developed a CMOS-compatible deposition and laser crystallization process for the production of micro-electromechanical systems (MEMS). In contrast to other common processes, the method eliminates the need for wires and solder joints — an advantage that can significantly reduce the component size and enhance the sensor performance.
To measure acceleration and other factors, MEMS inertial sensors are incorporated into consumer products such as smartphones, smartwatches, quadrocopters, and other devices. For the MEMS sensor units to perform these tasks safely and reliably, they are combined with an electronic, application-specific integrated circuit (ASIC) that sits on a silicon carrier unit (wafer).
Fraunhofer ILT, together with Fraunhofer ISIT and IST, has developed a selective, laser-based crystallization process for the manufacture of MEMS sensor units directly on active circuits. Courtesy of Fraunhofer ILT.
However, because the ambient temperature near the integrated circuit with its temperature-sensitive CMOS transistors may not exceed 450 ºC, MEMS sensors made of crystalline silicon are first manufactured separately due to the conventionally high manufacturing temperatures. Then they are connected to the circuit via wire and solder connections or wafer bonding processes.
According to Florian Fuchs, a research associate in the Thin Film Processing group at Fraunhofer ILT, conventional interconnection technology requires a relatively large amount of space and prevents further miniaturization of the MEMS. For this reason, MEMS made of crystalline silicon cannot be built directly on the ASIC. The temperature incompatibilities in the manufacturing process make it difficult to further miniaturize the sensors and enhance their performance.
Fraunhofer ILT’s laser-based approach enabled the researchers to build MEMS sensors of crystalline monolithically on the temperature-sensitive circuits.
Detailed view of the silicon arrays selectively laser-crystallized by Fraunhofer ILT. Courtesy of Fraunhofer ILT.
The researchers took advantage of the fact that amorphous silicon layers can already be produced on the wafer holding the circuit at temperatures below 450 ºC and high deposition rates. The laser not only crystallizes this silicon layer, but it also activates the dopants it contains, ensuring suitable electrical conductivity.
Subsequently, the sensor units are processed further using classic microelectronic manufacturing processes.
When laser radiation is used to crystallize silicon at high temperature, but below its melting point, crystallization occurs spatially, selectively, and very quickly, in the lower millisecond range. This way — in conjunction with targeted temperature management — the process minimized mechanical stresses in the layer material but did not damage the sensitive electronics on the underlying substrate. The silicon is crystallized with a focused laser beam and guided by a mirror to scan the entire surface step by step. In this spatially selective process, heat is removed effectively in three spatial directions. This distinguishes the process from alternative photonic processes such as flash exposure, where heat can only be dissipated in one direction because the area to be processed is so large.
“Since the energy is quickly introduced into only a small volume, we achieve solid phase crystallization of the silicon with laser processing at temperatures that are actually above the destruction threshold of the underlying circuit. Due to the short local processing time, the circuit is nevertheless not damaged,” said Christian Vedder, head of the Thin Film Processing group at Fraunhofer ILT.
Process image of the selective laser crystallization process for silicon wafers developed by Fraunhofer ILT. Courtesy of Fraunhofer ILT.
The laser process reduced the electrical resistances of the silicon layers by more than four orders of magnitude, down to below a value of 0.05 Ω*cm. At a layer thickness of 10 µm, this value corresponds to a sheet resistance of 50 Ω/sq. MEMS sensors with typical finger structures for a capacitive acceleration sensor could be produced from these layers.
“As crystalline silicon layers can be produced under CMOS-compatible conditions on an ASIC wafer, we are opening up new possibilities for integrating MEMS-IC because it is no longer necessary to modify the CMOS manufacturing processes,” Fuchs said.
Since the process constraints have been eliminated, MEMS and ICs can be developed independently, thus potentially reducing development time and costs. In addition to increasing integration density, the process eliminates wire connections and bond pads, leading to expected lower parasitic interference variables and improved shielding against electromagnetic interference fields. This elimination, in turn, has a positive effect on the signal quality and drift behavior of the sensors.
The work has broad-reaching potential. For example, it could be adapted to the specific requirements of different sensor types with different layer thicknesses or other doping materials.