The Belgium-based research and innovation hub imec developed a virtual fab model that enables the hub and its partners to assess current manufacturing choices, identify areas of focus, and project the future of the environmental impact of semiconductor manufacturing processes. The goal is to foster practical solutions for reducing global carbon emissions resulting from the lithography and etch process steps.
The in-house virtual fab model was built within the imec.netzero software platform. Imec spotlighted the virtual fab at the 2023 SPIE Advanced Lithography + Patterning Conference in February as part of a quantitative assessment of the environmental impact of patterning in advanced integrated circuit (IC) manufacturing.
Carbon dioxide (CO2) emissions associated with IC manufacturing are expected to quadruple in the next decade due to both the increasing complexity of advanced technologies and the projected growth of the total volume of wafers produced. To counter this scenario, leading semiconductor companies have committed to becoming carbon neutral or net zero by 2030 to 2050.
In that context, imec launched its Sustainable Semiconductor Technologies and Systems (SSTS) program, gathering the supply chain to jointly target net-zero emissions for chip manufacturing.
One of the goals of the program is to offer the industry a unique bottom-up approach that provides actionable data with a high granularity enabling impact assessment during process and flow development.
Using imec.netzero, a modeling platform developed in the frame of the SSTS program, imec and its partners quantified the environmental impact of patterning-related process steps for various logic technology nodes.
The imec.netzero modeling platform. It functions as a virtual fab to deliver a quantified bottom-up view of integrated circuit manufacturing for various technologies, and it projects future environmental impacts of the manufacturing process. Imec.netzero can act as a standard to estimate energy consumption, water usage, mineral usage, and greenhouse gas emissions associated with the fabrication of present and future logic CMOS technologies. Courtesy of imec.
“By applying this ‘virtual fab’ tool, we demonstrated that lithography and etch together are responsible for 45% of the Scope 1 and Scope 2 emissions (i.e., emissions from owned or operated assets and from purchased energy, respectively) associated with fabricating 3-nm logic wafers,” said Emily Gallagher, a principal member of the technical staff at imec.
“In addition, the modeling tool can quantify the gains associated with real fab experiments. For example, lowering the EUV [extreme ultraviolet] dose by 10% saves about 0.4 kg CO2eq [carbon dioxide equivalent] per wafer,” she said. “This would result in saving about 40 tons of CO2eq per month in a large fab, equivalent to emissions associated with 100 round-trip flights from San Francisco, Calif., to Portland, Ore.”
Imec's physical lab functions as a pilot environment to explore process and design directions and environmentally friendly process solutions for so-called high-impact areas, including reducing fluorinated etch gases, maximizing EUV scanner throughput, and reducing hydrogen and water consumption.
Imec and its partner Edwards recently installed a hydrogen recovery system for EUV lithography in imec's 300-mm cleanroom, enabling the reuse and recovery of about 70% of the hydrogen.
“Additionally, we are increasing focus on low-dose solutions for both 0.33 NA and 0.5 NA (high NA) EUV lithography, an effort that is also known to reduce costs in lithography,” Gallagher said. “We also identified etch directions for improved sustainability, currently focusing on overall reduction of conventional gas consumption.”
Steven Scheer — senior vice president of advanced patterning, process, and materials at imec — said, “The patterning process steps developed in the past have largely contributed to the semiconductor revolution, and further advancements are essential to keep pace with the demand for ever-increasing compute performance.”
Defining strategies to reduce CO2 emissions, while keeping the same patterning capabilities, will be a significant undertaking, according to Scheer. Further, he said, not all environmental impact is captured, or gauged, in the carbon-equivalent emission metric.
“For example," Scheer said, "gas emissions can be hazardous air pollutants (HAPS), and both photoresists and antireflection coatings (ARCs) can contain PFAS (perfluoroalkyl and polyfluoroalkyl substances). The carbon-fluoride bond strength of PFAS has contributed to the superior performance characteristics of chemically amplified resists (CARs) for both mature optical and evolving EUV photoresists. However, its bioaccumulation potential has led to a strong societal interest to eliminate their use.”
According to Scheer, projects that consider PFAS elimination must be considered in addition to those that lower carbon emissions directly.
Imec.netzero could act as a standard for estimating energy consumption, water usage, mineral usage, and greenhouse gas emissions associated with the fabrication of present and future logic CMOS technologies. The platform is aimed to deliver a quantified, bottom-up view of integrated circuit manufacturing for various technologies, including future ones.