The Universal Chiplet Interconnect Express (UCIe) Consortium has released its 2.0 Specification. The UCIe 2.0 Specification adds support for a standardized system architecture for manageability and holistically addresses the design challenges for testability, manageability, and debug (DFx) for the system-in-package (SIP) lifecycle across multiple chiplets — from sort to management in the field. “[The] UCIe Consortium is supporting a diverse range of chiplets to meet the needs of the rapidly changing semiconductor industry,” said Cheolmin Park, UCIe Consortium president and corporate vice president of Samsung Electronics. According to Park, the newly unveiled specification builds on previous iterations, both by developing a comprehensive solution stack, as well as by further encouraging interoperability between distinct chiplet solutions. The introduction of optional manageability features and a UCIe DFx Architecture (UDA), which includes a management fabric within each chiplet for testing, telemetry, and debug functions — allows vendor agnostic chiplet interoperability across a flexible and a unified approach to SIP management and DFx operations. Additionally, the 2.0 Specification supports 3D packaging, offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. UCIe-3D is optimized for hybrid bonding with a bump pitch functional for bump pitches from 10 to 25 µm down to 1 µm or less to provide flexibility and scalability. Another feature is optimized package designs for interoperability and compliance testing: The goal of compliance testing is to validate the main-band supported features of a device under test against a known-good reference UCIe implementation. UCIe 2.0 establishes an initial framework for physical, adapter, and protocol compliance testing. “The UCIe 2.0 specification is critical for the interconnect chiplet ecosystem and sets the stage for unleashing next-gen AI architectures,” said LK Bhupathi, Ayar Labs’ vice president of products, strategy, and ecosystem, in a statement. Ayar Labs is a contributing member of the consortium and has centered its TeraPHY optical input/output (I/O) chiplet roadmap around the UCIe specification, Bhupathi said. “The UCIe Consortium’s work is instrumental in driving broad adoption and manufacturability of optical I/O to deliver the high bandwidth, energy efficiency, and low latency required for AI innovation and application growth.” The UCIe Consortium is an industry consortium dedicated to advancing UCIe technology, an open industry standard that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. UCIe Consortium is led by key industry leaders Advanced Semiconductor Engineering, Inc, Alibaba, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, NVIDIA, Qualcomm Incorporated, Samsung Electronics, and Taiwan Semiconductor Manufacturing Company, and represents more than 130 member companies. The UCIe 2.0 Specification is available by request at www.uciexpress.org/specifications.