Photonics Spectra BioPhotonics Vision Spectra Photonics Showcase Photonics Buyers' Guide Photonics Handbook Photonics Dictionary Newsletters Bookstore
Latest News Latest Products Features All Things Photonics Podcast
Marketplace Supplier Search Product Search Career Center
Webinars Photonics Media Virtual Events Industry Events Calendar
White Papers Videos Contribute an Article Suggest a Webinar Submit a Press Release Subscribe Advertise Become a Member


Joint imec-ASML Lithography Lab Reports Breakthroughs

imec and ASML have demonstrated the utility of the 0.55 numerical aperture (NA) extreme ultraviolet (EUV) scanner in the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, Netherlands. imec reported that it successfully patterned single exposure random logic structures with 9.5 nm dense metal lines, corresponding to a 19 nm pitch, achieving sub 20 nm tip-to-tip dimensions. The R&D center additionally reported printing random vias with a 30 nm center-to-center distance, 2D features at a P22 nm pitch, and dynamic random access memory (DRAM)-specific layout at P32 nm.

The results, imec said, were printed after single exposure, using materials and baseline processes that were optimized for high NA EUV in the framework of imec’s Advanced Patterning Program.

Following the lab’s recent opening, customers now have access to the TWINSCAN EXE:5000 High NA EUV scanner to develop private High NA EUV use cases leveraging the customer’s own design rules and layouts.
The 9.5 nm random logic structure (19 nm pitch) after pattern transfer. Courtesy of imec.
“The results showcase the unique potential for High NA EUV to enable single-print imaging of aggressively-scaled 2D features, improving design flexibility as well as reducing patterning cost and complexity,” said Steven Scheer, senior vice president of compute technologies and systems/compute system scaling at imec. “Looking ahead, we expect to provide valuable insights to our patterning ecosystem partners, supporting them in further maturing High NA EUV specific materials and equipment.”

The successful patterning of designs that integrate the storage node landing pad with the bit line periphery for DRAM — beyond logic structures —underscores the potential of High NA technology to replace the need of several mask layers by a single exposure, imec said.

Explore related content from Photonics Media




LATEST NEWS

Terms & Conditions Privacy Policy About Us Contact Us

©2024 Photonics Media