A chip-based source for terahertz power could improve the efficiency of electronic devices and chip-based applications. But generating terahertz waves on a semiconductor chip is difficult. To meet this challenge, a team at MIT created a chip-based, terahertz amplifier-multiplier system that achieves high radiating power within a streamlined design. The compact device for generating terahertz on a chip could be used to improve data transmission, medical imaging, high-resolution radar, environmental monitoring, and many other applications. One approach to generating terahertz waves on a chip is to use a CMOS, chip-based amplifier-multiplier chain that increases the frequency of radio waves until the waves reach the terahertz range. The waves pass through the silicon chip and are emitted into the open air. However, the amount of terahertz radiation that is either absorbed, reflected, or transmitted is affected by the dielectric constant. Since the dielectric constant of silicon is higher than that of air, most terahertz waves are reflected at the silicon-air boundary, instead of being transmitted. Most of the terahertz signal strength is lost at this boundary, and silicon lenses are often used to boost the power of the remaining signal. These lenses, which can be larger than the chip itself, make it hard to integrate the terahertz source into an electronic device. The MIT researchers took a different approach. They used a matching material to equalize the dielectric constants of silicon and air. The researchers attached a thin sheet of material with a dielectric constant between silicon and air to the back of the chip. The matching sheet increased terahertz wave transmission and reduced the reflection of terahertz waves. As a result, the team was able to minimize the loss of signal strength at the boundary. By affixing a thin, patterned sheet of material to the back of the chip, highlighted in the center and shown in the left-side micrograph, the researchers produced an efficient, yet scalable, chip-based terahertz wave generator. Courtesy of J. Wang, D. Sheen, X. Chen, S.F. Nagle, R. Han/MIT News. For the matching component, the researchers chose a low-cost, commercially available substrate material with a dielectric constant that was close to what they needed. With a laser cutter, they punched tiny holes into the material to tailor its dielectric constant to fit their needs. “Since the dielectric constant of air is 1, if you just cut some subwavelength holes in the sheet, it is equivalent to injecting some air, which lowers the overall dielectric constant of the matching sheet,” researcher Jinchen Wang said. To further improve performance, the researchers included transistors developed by Intel in the chip’s design. The Intel transistors have a higher maximum frequency and breakdown voltage than traditional CMOS transistors. “These two things taken together, the more powerful transistors and the dielectric sheet, plus a few other small innovations, enabled us to outperform several other devices,” Wang said. The chip demonstrated the ability to generate terahertz signals with a peak radiation power of 11.1 decibel-milliwatts, achieving higher terahertz radiating power than existing state-of-the-art techniques. The chip can be fabricated at scale. To ensure scalability, the researchers had to determine how the chip would manage power and temperature when generating terahertz waves. “Because the frequency and the power are so high, many of the standard ways to design a CMOS chip are not applicable here,” Wang said. The team also needed to devise a scalable technique for installing the matching sheet at a manufacturing facility. “To take full advantage of a terahertz wave source, we need it to be scalable,” Wang said. “Here we’ve demonstrated a promising approach that can be used for scalable, low-cost terahertz arrays.” The researchers plan to demonstrate the chip’s scalability by fabricating a phased array of CMOS terahertz sources that will enable them to focus a powerful terahertz beam with a low-cost, compact device. The research was presented at the IEEE International Solid-State Circuits Conference (ISSCC), Feb. 16-20, 2025, in San Francisco.