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Memory Design Charts a Course for Scalability

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MADISON, Wis., Dec. 8, 2025 — A team at the University of Wisconsin-Madison, working in collaboration with researchers at the University of Southern California Information Sciences Institute, has developed and tested an integrated photonic memory chip that it believes could soon bring optical computing connectivity to data centers and high-performance computing systems. The chip leverages parts and fabrication techniques currently used by established semiconductor foundries.

“This memory can store light and operate at speeds beyond the reach of its electrical counterpart memory,” said Akhilesh Jaiswal, a UW-Madison assistant professor of electrical and computer engineering. “This is the first ever solution that provides a viable pathway to a scalable photonic memory on a commercial foundry process that can be volume-manufactured right away.”

University of Wisconsin-Madison assistant professor of electrical and computer engineering Akhilesh Jaiswal and Md Abdullah-Al Kaiser. Courtesy of UW-Madison/Joel Hallberg.
University of Wisconsin-Madison assistant professor of electrical and computer engineering Akhilesh Jaiswal (left) and Md Abdullah-Al Kaiser. Courtesy of UW-Madison/Joel Hallberg.

As computing power has increased, so has their need for electricity. Optical computing has emerged as a way to alleviate that, but researchers are still figuring out optical analogues of all the necessary computer components. Currently, most optical systems are electrical/optical hybrids, in which signals are converted from light to electricity and back again, negating some of the advantages.

One critical component with no immediate practical optical alternative is memory, where information is stored or buffered before reaching a computer processor. Of the many possible solutions that researchers have developed, most have tradeoffs when it comes to size, speed, energy use or compatibility with existing manufacturing processes that make them difficult to scale.

Jaiswal and his collaborators, however, created a photonic memory using a design they call a “cross-coupled, differential, regenerative photonic latch” (pLatch) circuit. This novel component uses a combination of tiny photodiodes, micro-ring resonators and optical waveguides. Together, the devices create an optical analog of SRAM, the type of memory used in electricity-based computer processors.

“In principle, it has all the same capabilities of the electrical SRAM, but is much faster,” said Jaiswal. “An electrical SRAM operates at two or three gigahertz. In our simulations, we see the pLatch operate at 20 GHz, and the read speed could be 50 or 60 GHz.”

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A key drawback to the device, and one that affects photonic components in general, is its size. While electronic computer components have shrunk to the nanoscale — used to describe the size of atoms — photonics are still at the micro level, the scale used to measure the thickness of a sheet of paper.

The size means optical computing cannot currently power processors inside cellphones or desktop computers. As large optical “interposers,” however, they are useful in linking many different processors. They can be used to tie together racks of servers in data centers to help them work in unison, and they offer a similar function in bringing optical speeds to the multi-processor systems used for high-performance computing and large-scale simulations.

While finding a unique solution to the optical computing bottleneck is an achievement, the team thinks the most important part of its circuit is its practicality. The researchers developed the design in consultation with cutting-edge chip fabrication firms AIM Photonics and GlobalFoundries, using their silicon photonics platform to fabricate the pLatch device.

“Our solution only uses those components that are currently available in a commercial foundry,” said Jaiswal.

The Wisconsin Alumni Research Foundation has already helped the team secure several patents for the technology, and it is helping Jaiswal commercialize the technology.

The work is to be presented at the International Electron Devices Meeting.

Published: December 2025
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