In a bid to boost domestic capacity for semiconductor advanced packaging, the U.S. Department of Commerce has issued a notice of intent to open a competition for new R&D activities. The CHIPS for America program anticipates up to $1.6 billion in funding will be spread across five R&D areas outlined in the National Advanced Packaging Manufacturing Program spearheaded by the National Institute of Standards and Technology. Through potential cooperative agreements, CHIPS for America would make several awards of approximately $150 million available per award in each research area. Funded R&D areas include equipment, tools, processes, and process integration; power delivery and thermal management; connector technology, including photonics and radio frequency; chiplets ecosystem; and co-design/electronic design automation. For photonics and connectors, funding will target the development of components geared toward communication with low error rates, high-density, high speed, and low loss to manage long haul communications. In equipment, tools and processes, the program aims to adapt CMOS equipment and processes to allow them to handle dies and wafers compatible with different types of substrates. Semiconductor Packaging Semiconductor packaging serves two general purposes. The first is to protect the chip mechanically, thermally, and environmentally. The second is to facilitate reliable interchip communication, deliver power, and provide a stable test and system integration platform. Advanced packaging and capabilities such as heterogeneous integration encompass the need to integrate multi-component assemblies with large numbers of interconnects. This method achieves a degree of integration that blurs the line between chip and package by tightly assembling multiple chips together on a substrate in two or three dimensions at extremely fine dimensions. The method enables semiconductor manufacturers to make improvements in system performance and production, as well as to reduce the time to market. Further benefits include a reduced physical footprint, lower power requirements, decreased costs, and increased chiplet reuse.
