Integration Method Efficiently Couples III-V with Silicon

In the past decades, data traffic has grown exponentially driven by emerging technologies. The field of integrated circuits has enabled that growth, making electronic devices smaller and faster. But the start of the Zettabyte Era in 2016 has pushed the technology to its limits, posing critical challenges in speed, bandwidth, cost, and power consumption. Photonic integration, particularly silicon photonics, presents an opportunity to alleviate those challenges.

Researchers at the Hong Kong University of Science and Technology (HKUST) have developed an integration technique for efficient coupling of III-V compound semiconductor devices and silicon, paving the way for photonic integration at low cost, large volume, and high speed and throughput that could significantly impact data communications.

While silicon can handle passive optical functions, it struggles with active tasks, such as generating light or detecting it — both key components for data generation and readout. This necessitates the integration of a III-V semiconductor onto a silicon substrate for complete functionality and enhanced efficiency.

Xue Ying (shown), research assistant professor at Hong Kong University of Science and Technology, led research which demonstrated an efficient integration technique for the coupling of III-V semiconductors with silicon, paving the way for critical applications in a variety of fields, including supercomputing, AI, biomedicine, automotive applications, and neural and quantum networks. Courtesy of HKUST.

Although III-V semiconductors do the active tasks well, they do not naturally work well with silicon. Previously reported integration methods have struggled to produce a method that enables both high coupling efficiency and high production volume.

The team at HKUST, led by research professors Xue Ying and Lau Kei-May, developed a technique called lateral aspect ratio trapping (LART) — a novel selective direct epitaxy method that can selectively grow III-V materials on silicon-on-insulator (SOI) in a lateral direction without the need for thick buffers.

“Our approach addressed the mismatch of III-V devices and Si. It achieved excellent performance of III-V devices and made it easy and efficient to couple III-V with Si,” Ying said.

The method achieved an in-plane III-V laser, allowing for efficient coupling between III-V lasers and silicon waveguides.

The unique III-V-on-insulator structure also provides strong optical confinement for the lasers. Gratings are designed and fabricated with minimal non-radiative recombination and a simple process with good tolerance.

The method is expected to enable a variety of technologies, applications, and research areas, including supercomputing, AI, biomedicine, automotive applications, and neural and quantum networks.

However, there are key scientific challenges to address before this technique can be implemented in practical applications, Ying said.

In the next steps, the team plans to show that III-V lasers integrated with silicon waveguides can perform well, as in having a low threshold, high output power, long lifetime, and the ability to operate at high temperatures.

Ying recently received a grant worth $100,000 from the 2023 Optica Foundation Challenge for her innovations in mitigating the limitations associated with photonic integrated circuits. The grant will be used to advance her research.

The research was published in Laser & Photonics Reviews (www.doi.org/10.1002/lpor.202300549).