Team Deepens Understanding of IC-PIC Integration's Thermal Penalty

Co-packaged optics for high performance computing and other data center applications require dense integration of silicon PICs with electronic integrated circuits (EICs). Stacking an electronic chip on top of a photonic chip allows for a tight integration of the components necessary to convert data from the electrical to the optical domain with low parasitic capacitance.

However, 3D integration comes with a stiff thermal penalty and the silicon (Si) photonic chips used to convert electrical data into the optical domain are highly sensitive to temperature changes. These modulators require active thermal tuning for stable operation in a demanding environment like a data center. Thermal stabilization is provided via integrated heaters.

Researchers at KU Leuven and imec investigated the impact of 3D hybrid integration on the thermal performance of Si ring-based photonic devices in wavelength-division multiplexing photonic integrated circuits (PICs). They quantified the thermal impact of 3D photonic-electronic integration and looked at potential approaches to prevent the loss of heater efficiency.

A hybrid, 3D integrated optical transceiver. (A and B): The test setup: the photonic integrated circuit (PIC) is placed on a circuit board (green), and the electronic integrated circuit (EIC) is bonded on top of the photonic circuit. A cross-section of the EIC-PIC assembly with µbumps (C). The mesh of the finite element model (D). Courtesy of David Coenen, Minkyu Kim, Herman Oprins, Yoojin Ban, Dimitrios Velenis, Joris Van Campenhout, Ingrid De Wolf, doi: 10.1117/1.JOM.4.1.011004.

Because the thermal behavior of 3D EIC-PIC integration can have a significant impact on the efficiency of the device, it is necessary to find ways to minimize the thermal impact of 3D stacking photonic and electronic chips.

The researchers investigated the efficiency of the integrated heaters and the thermal crosstalk between them. They carried out experiments with and without EIC flip-chipped on top of the PIC with μbumps, for ring modulators with and without substrate undercut (UCUT). They used the experimental results to validate finite element models. They calibrated the models with thermo-optic device measurements both before and after flip-chip bonding the EIC on the PIC.

Based on their analysis of the experimental results, the researchers concluded that the heater efficiency was decreased with 43.3% after EIC integration with μbumps, and that the decrease had a significant effect on overall thermal tuning energy consumption. From their simulation results, the researchers concluded that the undesirable impact on the thermal performance of the heaters was caused by the heat conduction and spreading inside the EIC.

The team determined that a thermally aware design with an additional gap between the ring modulator and μbumps and a smaller copper (Cu) linewidth could largely offset the loss in heater efficiency.

The researchers also used the calibrated finite element model to simulate thermal crosstalk with and without EIC. The addition of the EIC increased thermal crosstalk with 44.4%. The team found that if the transceiver was cooled by a liquid cooled cold plate on the top side, thermal crosstalk could be lowered with a factor of 2.

The integration of the EIC is instrumental for low electrical parasitics and good radio frequency (RF) performance from the transceiver. However, based on their findings, the researchers believe that the thermal behavior of 3D EIC-PIC integration must be carefully monitored, as the close integration of the EIC, without thermal mitigation strategies, can cause a heat spreading effect that reduces heater efficiency and increases thermal coupling.

The research was published in the Journal of Optical Microsystems (www.doi.org/10.1117/1.JOM.4.1.011004).