Intel Establishes Integrated Photonics Research Center

Intel Labs has opened the Intel Research Center for Integrated Photonics for Data Center Interconnects. The center’s mission is to accelerate optical input/output (I/O) technology innovation in performance scaling and integration with a specific focus on photonics technology and devices, CMOS circuits and link architecture, and package integration and fiber coupling.

Seven researchers are participating in the center, which Intel said brings together universities and researchers to accelerate optical I/O technology innovation in performance scaling and integration. The research vision is to explore a technology scaling path that satisfies energy efficiency and bandwidth performance requirements for the next decade and beyond, Intel said.

The researchers participating in the Intel Research Center follow:

John Bowers, University of California, Santa Barbara (UCSB).
Project: Heterogeneously integrated quantum dot lasers on silicon.

Description: The UCSB team will investigate issues with integrating indium arsenide (InAs) quantum dot lasers with conventional silicon photonics. The goal of this project is to characterize expected performance and design parameters of single-frequency and multiwavelength sources.

Pavan Kumar Hanumolu, University of Illinois, Urbana-Champaign.
Project: Low-power optical transceivers enabled by duo-binary signaling and baud-rate clock recovery.

Description: This project will develop ultralow-power, high-sensitivity optical receivers using novel trans-impedance amplifiers and baud-rate clock and data-recovery architectures. The prototype optical transceivers will be implemented in a 22-nm CMOS process to demonstrate very high jitter tolerance and excellent energy efficiency.

Arka Majumdar, University of Washington (UW).
Project: Nonvolatile reconfigurable optical switching network for high-bandwidth data communication.

Description: The UW team will work on low-loss, nonvolatile, electrically reconfigurable, silicon photonic switches using emerging chalcogenide phase change materials. Unlike existing tunable mechanisms, the developed switch will hold its state, allowing zero static power consumption.

Samuel Palermo, Texas A&M University.
Project: Sub-150 fJ/b optical transceivers for data center interconnects.

Description: This project will develop energy-efficient optical transceiver circuits for a massively parallel, high-density, and high-capacity photonic interconnect system. The goal is to improve energy efficiency by employing dynamic voltage frequency scaling in the transceivers, low-swing voltage-mode drivers, ultrasensitive optical receivers with tight photodetector integration, and low-power optical device tuning loops.

Alan Wang, Oregon State University.
Project: 0.5-V silicon microring modulators driven by high-mobility transparent conductive oxide.

Description: This project seeks to develop a low-driving-voltage, high-bandwidth, silicon microring resonator modulator (MRM) through heterogeneous integration between the silicon MOS capacitor with high-mobility Ti:In₂O₃. The device promises to overcome the energy-efficiency bottleneck of the optical transmitter and can be co-packaged in future optical I/O systems.

Ming Wu, University of California, Berkeley.
Project: Wafer-scale optical packaging of silicon photonics.

Description: The UC Berkeley team will develop integrated waveguide lenses that have potential to enable noncontact optical packaging of fiber arrays with low loss and high tolerances.

S.J. Ben Yoo, University of California, Davis.
Project: Athermal and power-efficient scalable high-capacity silicon-photonic transceivers.

Description: The UC Davis team will develop extremely power-efficient athermal silicon-photonic modulator and resonant photodetector photonic integrated circuits scaling to 40-Tb/s capacity at 150-fJ/b energy efficiency and 16-Tb/s/mm I/O density. To achieve this, the team will also develop a new 3D packaging technology for vertical integration of photonic and electronic integrated circuits with 10,000 pad-per-square-mm interconnect pad density.