Toshiba Develops 32nm CMOS Platform Tech

Toshiba Corp. of Tokyo has announced a cost-effective 32-nm CMOS platform technology that offers higher density and improved performance while halving the cost per function from 45-nm processes. The platform was created by applying single-exposure lithography and gate-first metal gate/high-K process technology. It enables a 0.124 µm² SRAM cell and a gate density of 3650 gate/mm². The platform is based on a 32-nm process developed jointly with NEC Electronics Corp. The strict design rule in the 32-nm generation was originally seen as requiring dual exposure technology in the lithography process, which would result in higher process costs due to increased steps, and in degraded manufacturing yields owing to increased process dusts. Toshiba realized an architecture based on single-exposure lithography by applying ArF immersion lithography with a NA 1.3 and over, and by optimizing the lithography illumination conditions. The development work also demonstrated that application of a metal gate/high-K not only boosts transistor performance but also reduces threshold voltage mismatch. In addition, a bent-shaped type cell was selected for layout optimization, which also contributed to reduce threshold voltage mismatch. By adopting this approach, Toshiba said it realized a 32-nm CMOS platform design that reduces cost per function by 50 percent over 45 nm.