The objective of the proposal is to establish the necessary technology infrastructure associated with the S-FIL process, including system, materials and template (mask) development. The three-year project will focus on dense contact layers, which are critical in silicon integrated circuit fabrication. The $36 million award includes $17.6 million from NIST and $19.1 million from the joint venture participants.
S.V. Sreenivasan, co-founder and CTO of MII, said the project will help demonstrate how S-FIL technology can address the demanding requirements of silicon CMOS lithography.
MII's lithography systems and technology are used for manufacturing applications in the areas of nanodevices, microstructures, advanced packaging, biotechnology devices, optical components and semiconductor devices.
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